View CY62256_320472.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fax id: 1068
CY62256 32Kx8 Static RAM
Features
* 4.5V-5.5V Operation * Low active power (70 ns, LL version) -- 275 mW (max.) * Low standby power (70 ns, LL version) -- 28 W (max.) * 55, 70 ns access time * Easy memory expansion with CE and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected * CMOS for optimum speed/power output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. The CY62256 is in the standard 450-mil-wide (300-mil body width) SOIC, TSOP, and 600-mil PDIP packages. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.
Functional Description
The CY62256 is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW
Logic Block Diagram
Pin Configurations
SOIC/DIP Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
C62256-2
INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A 14 A 13
C62256-1
I/O0 I/O1
ROW DECODER
SENSE AMPS
I/O2 I/O3 I/O4 I/O5
512x512 ARRA Y
COLUMN DECODER A 12 A 11 A1 A0
POWER DOWN
I/O6 I/O7
A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE
7 6 5 4 3 2 1 28 27 26 25 24 23 22
TSOP I Reverse Pinout Top View (not to scale)
8 9 10 11 12 13 14 15 16 17 18 19 20 21
A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0
C62256-4
OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11
22 23 24 25 26 27 28 1 2 3 4 5 6 7
21 20 19 18 17 16 15 14 13 12 11 10 9 8
TSOP I Top View (not to scale)
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12
C62256-3
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 March 1996 - Revised November 26, 1997
CY62256
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied ................................................... 0C to +70C Supply Voltage to Ground Potential (Pin 28 to Pin 14).................................................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................... -0.5V to VCC + 0.5V DC Input Voltage[1] .................................... -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
CY62256-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 L LL L LL L LL Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA 2.2 -0.5 -0.5 -0.5 28 25 25 0.5 0.4 0.3 1 2 0.1 0.1 Min. 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 55 50 50 2 0.6 0.5 5 50 5 10 2.2 -0.5 -0.5 -0.5 28 25 25 0.5 0.4 0.3 1 2 0.1 0.1 Typ[2] Max. Min. 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 55 50 50 2 0.6 0.5 5 50 5 10 CY62256-70 Typ[2] Max. Unit V V V V A A mA mA mA mA mA mA mA A A A
ISB1
Automatic CE Power-Down Current-- TTL Inputs Automatic CE Power-Down Current-- CMOS Inputs
ISB2
Indust'l Temp Range LL
Shaded area contains preliminary information.
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 6 8 Unit pF pF
Note: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. 3. Tested initially and after any design or process changes that may affect these parameters.
2
CY62256
AC Test Loads and Waveforms
R1 1800 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE R2 990 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 990 3.0V 10% GND < 5 ns R1 1800 ALL INPUT PULSES 90% 90% 10% < 5 ns
C62256-6
C62256-5
(a)
Equivalent to: THE VENIN EQUIVALENT 639 OUTPUT 1.77V
(b)
Data Retention Characteristics
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current L LL LL Indust'l tCDR[3] tR[3] Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC Conditions[4] VCC = 3.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Min. 2.0 2 0.1 0.1 50 5 10 Typ.[2] Max. Unit V A A A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE
C62256-7
VDR > 2V
3.0V tR
Note: 4. No input may exceed VCC+0.5V.
3
CY62256
Switching Characteristics Over the Operating Range[5]
CY62256-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[8, 9]
CY62256-70 Min. 70 Max. Unit ns 70 5 70 35 5 25 5 25 0 70 70 60 60 0 0 50 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 5 ns ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z
[6, 7] [6] [6, 7]
Min. 55
Max.
55 5 55 25 5 20 5 20 0 55 55 45 45 0 0 40 25 0 20 5
CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z
[6, 7]
WE HIGH to Low Z[6]
Shaded area contains preliminary information.
Switching Waveforms
Read Cycle No. 1 [10,11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
C62256-8
Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle.
4
CY62256
Switching Waveforms (continued)
Read Cycle No. 2 [11,12]
CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB
C62256-9
tRC
tHZOE tHZCE DATA VALID
HIGH IMPEDANCE
DATA OUT
[8,13,14]
Write Cycle No. 1 (WE Controlled)
tWC ADDRESS
CE tAW WE tSA tPWE tHA
OE tSD DATA I/O NOTE 15 tHZOE
[8,13,14]
tHD
DATAIN VALID
C62256-10
Write Cycle No. 2 (CE Controlled)
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAIN VALID
C62256-11
tSCE
tHA
tHD
Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
5
CY62256
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[9,14]
tWC ADDRESS
CE tAW WE tSA tHA
tSD DATA I/O NOTE 15 tHZWE
Note: 15. During this period, the I/Os are in output state and input signals should not be applied.
tHD
DATAIN VALID tLZWE
C62256-12
6
CY62256
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4
SB
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.4 1.2 NORMALIZED I CC ICC 3.0 2.5 2.0 ISB2 A 1.5 1.0 0.5 0.0 25 125 -0.5
STANDBY CURRENT vs. AMBIENT TEMPERATURE
1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN =5.0V TA =25C ICC
NORMALIZED ICC, I
1.0 0.8 0.6 0.4 0.2 0.0 VCC =5.0V VIN =5.0V
ISB
VCC =5.0V VIN =5.0V 25 105
-55
-55
SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA
AA
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT SINK CURRENT (mA) 1.6 1.4 1.2 1.0 VCC =5.0V 0.8 0.6 140 120 100 80 60 40 20 0 0.0
AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
1.3 1.2 1.1 TA =25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0
NORMALIZED t
VCC =5.0V TA =25C
-55
25
125
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT (mA)
AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
7
CY62256
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 DELTA tAA (ns)
PO
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 NORMALIZED ICC 25.0 20.0 15.0 10.0 5.0 VCC =4.5V TA =25C 1.25
NORMALIZED I CC vs.CYCLE TIME
2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0
NORMALIZED I
1.00
VCC =5.0V TA =25C VIN =0.5V
0.75
0.0
0
200
400
600
800 1000
0.50 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect, Output Disabled Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
8
CY62256
Ordering Information
Speed (ns) 55 Ordering Code CY62256-55SNC CY62256L-55SNC CY62256LL-55SNC CY62256-55ZRC CY62256L-55ZRC CY62256LL-55ZRC CY62256-55ZC CY62256L-55ZC CY62256LL-55ZC CY62256-55PC 70 CY62256-70SNC CY62256L-70SNC CY62256LL-70SNC CY62256-70SNI CY62256L-70SNI CY62256LL-70SNI CY62256-70ZC CY62256L-70ZC CY62256LL-70ZC CY62256-70ZI CY62256L-70ZI CY62256LL-70ZI CY62256-70PC CY62256L-70PC CY62256LL-70PC CY62256-70ZRC CY62256L-70ZRC CY62256LL-70ZRC
Shaded area contains preliminary information.
Package Name S22 S22 S22 ZR28 ZR28 ZR28 Z28 Z28 Z28 P15 S22 S22 S22 S22 S22 S22 Z28 Z28 Z28 Z28 Z28 Z28 P15 P15 P15 ZR28 ZR28 ZR28
Package Type 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead Reverse Thin Small Outline Package 28-Lead Reverse Thin Small Outline Package 28-Lead Reverse Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead (600-Mil) Molded DIP 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead (600-Mil) Molded DIP 28-Lead (600-Mil) Molded DIP 28-Lead (600-Mil) Molded DIP 28-Lead Reverse Thin Small Outline Package 28-Lead Reverse Thin Small Outline Package 28-Lead Reverse Thin Small Outline Package
Operating Range Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Document #: 38-00455-C
9
CY62256
Package Diagrams
28-Lead (600-Mil) Molded DIP P15
28-Lead 450-Mil (300-Mil Body Width) SOIC S22
10
CY62256
Package Diagrams (continued)
28-Lead Thin Small Outline Package Z28
11
CY62256
Package Diagrams (continued)
28-Lead Reverse Thin Small Outline Package ZR28
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

▲Up To Search▲

Price & Availability of CY62256

	To Download CY62256 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .